The present invention relates to an active matrix liquid crystal display having an improved thin film transistor (TFT) and related manufacturing method.
FIG. 1 illustrates a cross-sectional view of a conventional top gate-type TFT. In fabricating this kind of device, high impurity concentration source and drain regions 2a and 2b, respectively, are formed by ion implanting n or p conductivity type impurities using a gate electrode of the TFT as an implantation mask. As a result, the source and drain regions of the top gate-type TFT are said to be "self-aligned" with the gate electrode because the relative positions of the source and drain regions are determined by the gate electrode.
The self-aligned process used to fabricate the device shown in FIG. 1 is advantageous because it does not require any additional implantation masks, other than the gate electrode, to form source and drain regions 2a and 2b. Further, the self-alignment technique simplifies the overall manufacturing process because the source and drain regions are provided without additional photolithographic masking steps.
As shown in FIG. 1, the top gate-type TFT includes a channel region 1 between source region 2a and drain region 2b in polysilicon active layer 8. Active layer 8 and gate electrode insulating layer 3 are provided on substrate 7. Contact electrodes 6 are provided in contact holes through interlevel insulating film 5. In the TFT of FIG. 1, gate electrode 4 of the TFT overlies the entire length of channel region 1 and no portion of active layer 8 separates the source and drain regions 2a and 2b, respectively, from channel region 1.
The device shown in FIG. 1, however, can be fabricated with offsets or undoped regions separating the source and drain from the channel region. FIG. 2 is a graph illustrating drain current as a function of gate voltage for TFTs having offset lengths Loff of 0 microns, 0.5 microns and 1 micron, respectively.
The solid curve in FIG. 2 corresponds to the drain current characteristics of the conventional polysilicon TFT of FIG. 1. These leakage currents are due to electric field enhanced tunneling through traps in the drain junction. The leakage currents are generated even though the gate-source bias is negative, corresponding to the off-state of the TFT. Further, the leakage currents increase exponentially with increasingly negative gate-source voltage.
If the TFT shown in FIG. 1 is used as a switching device for driving pixels in a liquid crystal display, the signal voltage of the display will not be accurately maintained due to these high leakage currents. Consequently, flickering is observed in the liquid crystal display.
In order to solve these problems, a technique for forming lightly doped drains (LDDs) has been proposed. The LDD structure includes low-concentration impurity regions which are provided between the high impurity concentration drain region and the channel, as well as the high impurity concentration source region and the channel. The LDD is formed by providing additional masking steps and ion implantation processes.
Alternatively, undoped offset regions may be provided between the source/drain and the channel instead of LDD regions.
A conventional manufacturing process for fabricating a TFT having LDD or offset regions will be explained below with reference to FIGS. 3A to 3G.
As shown in FIG. 3A, active layer 12 is formed by patterning a thin-film of polysilicon on a substrate 11 using photolithographic and etching processes. FIG. 3B illustrates formation of gate insulating layer 13 on exposed portions of substrate 11 and active layer 12. Next, as shown in FIG. 3C, a metallic or doped polysilicon layer is provided on gate insulating layer 13 and patterned to form gate electrode 14.
LDD regions 15 are then formed by implanting n conductivity type impurity ions through gate insulating layer 13 into active layer 12 using gate electrode 14 as an implantation mask. If undoped offset regions are desired, however, the ion implantation step should be omitted.
In FIG. 3D, a masking insulating layer 16 (for instance, a photoresist layer) is provided on exposed surfaces of gate electrode 14 and gate insulating layer 13. Then, the insulating layer 16 is patterned to cover gate electrode 14 and LDD regions 15. Using the patterned insulating layer 16 as an ion-implantation mask, a high concentration of n conductivity type (n+) impurity ions are implanted into active layer 12 through gate insulating layer 13 to form source and drain regions 17a and 17b, respectively. As shown in FIG. 3E, insulating layer 16 is removed and, in FIG. 3F, an interlevel insulating layer 18 is formed on the entire exposed surface of gate electrode 14 and gate insulating layer 13. The interlevel insulating layer 18 and gate insulating layer 13 are then patterned to form contact holes 19a and 19b over portions of source and drain regions 17a and 17b, respectively.
As shown in FIG. 3G, a metal layer is deposited on the entire upper exposed surface of the interlevel insulating layer 18 and in contact holes 19a and 19b. The metal layer is then patterned to form contact electrodes serving as source electrode 20a and drain electrode 20b in contact holes 19a and 19b, respectively. The resulting structure shown in FIG. 3G includes a channel region 12a located under gate electrode 14 in active region 12.
However, the conventional TFT of FIG. 3G having LDD regions or offset regions has the following problems. As noted above, the LDD or offset regions are formed by patterning insulating layer 16 prior to implanting a low dose of impurities. The patterning is achieved by photolithographic processes in which a layer of photoresist is exposed with a desired pattern using a mask aligner. A device patterned properly will have a suitable characteristic as shown by the dot-dash line in FIG. 2.
Alignment errors generally occur, however, making it difficult to obtain the desired length of the LDD or offset region. If the length of the LDD or offset region is too short, a high leakage current flows in the drain region when the TFT is turned off. Thus, in order to fully suppress leakage current, the length of the LDD or offset region should be designed to be longer than the desired length.
If the length of the LDD or offset region significantly exceeds the desired value, however, drain on-current is reduced to an unacceptable level because the electrical resistance between the channel and source or drain increases significantly. Such a device is not suitable even though it has reduced leakage currents when it is turned off (see dotted line in FIG. 2).
Accordingly, the above described problems associated with conventional TFTs bring about non-uniformities in device characteristics across the substrate from manufacturing run to manufacturing run and from device to device. When the TFT is employed in a liquid crystal display, these nonuniformities deteriorate display performance and quality.